參數(shù)資料
型號: IC42S16400-7BIG
英文描述: 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
中文描述: 100萬× 16 × 4銀行(64兆位)內(nèi)存
文件頁數(shù): 26/68頁
文件大小: 1092K
代理商: IC42S16400-7BIG
IC42S16400
26
Integrated Circuit Solution Inc.
DR034-0E 12/02/2003
PRECHARGE TERMINATION
PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
When
CAS
latency is 2, the read data will remain valid until one clock after the precharge command.
When
CAS
latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
Burst lengh= X
CLK
Command
CAS latency=2
DQ
Hi-Z
Read
T0
T1
T2
T3
T4
T5
T6
T7
T8
PRE
ACT
DQ
Read
PRE
ACT
t
RP
CAS latency=3
Q0
Q3
Q2
Q1
Hi-Z
Q0
Q3
Q2
Q1
command
t
RP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IC42S16400-7T 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400-7TG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400-7TI 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400-7TIG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400A 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM