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| 型號： | IBMN364804CT3C-260 |
| 英文描述： | x8 SDRAM |
| 中文描述： | x8 SDRAM內(nèi)存 |
| 文件頁數(shù)： | 21/71頁 |
| 文件大?。?/td> | 1251K |
| 代理商： | IBMN364804CT3C-260 |
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IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 21 of 71
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it
can be interrupted by a Read or Write Command to a different bank. If the command is issued before auto-
precharge begins then the precharge function will begin with the new command. The bank being auto-pre-
charged may be reactivated after the delay t
.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ
contention.
Burst Read with Auto-Precharge Interrupted by Read
Burst Read with Auto-Precharge Interrupted by Write
t
RP
COMMAND
NOP
*
NOP
NOP
NOP
Auto-Precharge
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
t
RP
t
CK2,
DQs
CAS latency = 2
t
CK3,
DQs
CAS latency = 3
DOUT A
0
DOUT A
1
NOP
DOUT A
0
DOUT A
1
DOUT B
0
DOUT B
1
*
READ B
DOUT B
2
DOUT B
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
(Burst Length = 4, CAS Latency = 2, 3)
*
t
RP
is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Bank can be reactivated at completion of t
RP
.
COMMAND
NOP
NOP
*
NOP
Auto-Precharge
t
RP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
t
CK2,
DQs
CAS latency = 2
DQM
NOP
DOUT A
0
DOUT B
0
DOUT B
1
WRITE B
DOUT B
2
DOUT B
3
NOP
DOUT B
4
(Burst Length = 8, CAS Latency = 2)
*
t
RP
is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Bank can be reactivated at completion of t
RP
.
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| IBMN364804CT3C-360 | x8 SDRAM |
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