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參數(shù)資料
| 型號(hào)： | IBM39MPEGCS24 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Connector,Hybrid D-Shell,PCB Mnt,PLUG,12+5 Contacts,SKT,PC TAIL Terminal,HOLE .112-.124 |
| 中文描述： | CS24數(shù)字音頻/視頻解碼器 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大小： | 112K |
| 代理商： | IBM39MPEGCS24 |
IBM39MPEGS42x
IBM39MPEGSI
MPEG S422, MPEG S420 and MPEG SI Encoders
Sseries_sds_071701.fm.
02
July 17, 2001
SI Encoder Operations/Features
17 of 25
Active Picture Area
For NTSC, the 525 lines of video are broken into two active picture areas and two vertical blanking intervals. Lines
1-20 are a blanking interval, lines 21 through 262-1/2 are an active picture area, lines 262-1/2 through 282-1/2 are
a blanking interval, and lines 282-1/2 through 525 are an active picture area. Line 14 is used for time code
information, and line 21 contains closed caption information.
A common implementation uses lines 22-261 (240 lines) from the first active picture area and lines 285-524 (240
lines) from the second active picture area to comprise the 480 lines of a given picture. By starting 12 lines earlier
and ending four lines later than normal in each field, a 512-line picture can be created (e.g. lines 10-265 in the
digital odd field and lines 273-528 in the digital even field).
For PAL, the 625 lines of video are broken into two active picture areas and two vertical blanking intervals. Lines
624-625 and 1-22 are a blanking interval, lines 23 through 310 are an active picture area, lines 311-312-1/2 and
312-1/2-335 are a blanking interval, and lines 336 through 623 are an active picture area (i.e Lines 23 and 623 are
counted as ’full’ active lines).
Lines 23-310 (288 lines) from the first active picture area and lines 336-623 (288 lines) from the second active
picture area compose the 576 lines of a given picture.By starting 14 lines earlier and extending two lines later than
normal in each field, a 608-line picture can be created (e.g. lines 9-312 in the digital odd field and lines 322-625 in
the digital even field).
A feature is available in the S-Series encoders that provides the user with the flexibility to select the location of the
first active picture line by writing to Host Register X’1B’.
Encoder Latency
The delay between the first pixel data input at the video input interface and the availability of the first corresponding
compressed video data at the output interface is the encoder latency. The latency is due to the time required to
read all pixel data for a frame into the encoder, store it in frame memory, and process the data through the encoder.
The encoder latency is not fixed to a specific value and can change based on the encoding parameters (For
Input/Output Formats
Out
In
4:2:2 Interlaced
4:2:0 Interlaced
4:2:2
Progressive
4:2:0
Progressive
4:2:2 Field
Real time
*
Real time
*
4:2:0 Field
Real time (1)
Real time
Real time (1)
Real time
4:2:2 Frame
Real time
*
Real time
*
4:2:0 Frame
Real time (1)
Real time
Real time (1)
Real time
Note: (*) Not supported.
(1) Real time with 2-tap 4:2:2 to 4:2:0 filter
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| IBM39MPEGCS24DEPFA16C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CS24 Digital Audio/Video Decoders |
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