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5/20/99

Version 1.51

PowerPC 740 and PowerPC 750 Datasheet

Page 1

PowerPC 740 and PowerPC 750 Embedded Microprocessor

IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L

Preface

The PowerPC 740 and PowerPC 750 embedded microprocessors are implementations of the PowerPC

family of reduced instruction set computer (RISC) microprocessors. This document covers PowerPC 740 and

PowerPC 750 microprocessors using the IBM CMOS 7S 0.20 um copper technology. In this document, “740”

refers to the PowerPC 740 microprocessor, and “750” refers to the PowerPC 750 microprocessor, with the

document’s primary focus on the features of the 750 microprocessor; however, unless otherwise noted, all

features apply equally to the 740 microprocessor.

The 740 uses the same die as the 750, but the 740 does not pin out the L2 cache interface.

Overview

The 750 is targeted for high performance, low power systems and supports the following power management

features: doze, nap, sleep, and dynamic power management. The 750 consists of a processor core and an

internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus. The L2 cache is not available

with the 740.

Figure 1 shows a block diagram of the 750.

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