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參數(shù)資料
| 型號： | IBM25NPE405L-3FA266CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerNP |
| 中文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA324 |
| 封裝： | 23 X 23 MM, PLASTIC, EBGA-324 |
| 文件頁數(shù)： | 7/54頁 |
| 文件大?。?/td> | 460K |
| 代理商： | IBM25NPE405L-3FA266CZ |
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
5
NPe405L Embedded Controller Functional Block Diagram
The NPe405L is designed using the IBM Microelectronics Blue Logic
methodology in which major functional
blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way
to generate complex ASICs using IBM CoreConnect
Bus Architecture.
Address Map Support
The NPe405L incorporates two separate address maps. The first is a fixed processor address map that
serves the PowerPC family of processors. This address map defines the possible contents of various address
regions which the processor can access. The second address map is for Device Configuration Registers
(DCRs). The DCRs are accessed by software running on the NPe405L processor through the use of
mtdcr
and
mfdcr
commands.
PPC405
Processor Core
DCU
ICU
DCR Bus
16KB
I-Cache
On-chip Peripheral Bus (OPB)
GPIO
IIC
UART
x2
DMA
Controller
(4-Channel)
Bridge
Processor Local Bus (PLB)
SDRAM
Controller
External
Bus
Controller
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
OPB
Interrupt
Controller
x2
Arb
28-bit addr
16-bit data
13-bit addr
32-bit data
Universal
8KB
D-Cache
DCRs
See Peripheral Interface
Clock Timing table
MAL0
Ethernet
x2
HDLCEX
ZMII
MAL1
Two
32-channel
ports
MII,
RMII,
SMII
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