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參數(shù)資料
| 型號： | IA88C00-PLC68I-R-01 |
| 廠商： | Innovasic Semiconductor |
| 文件頁數(shù)： | 28/80頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 20MHZ 68PLCC |
| 標準包裝： | 285 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | EBI/EMI，UART/USART |
| 外圍設(shè)備： | DMA，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | 外部程序存儲器 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 管件 |
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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 34 of 80
1.888.824.4184
D4 - FERR - Framing Error - This is a status bit. If a framing error occurs (no stop bit where expected),
this bit is set for the receive character in which the framing error occurred. This bit remains set until
cleared to 0 by writing a 1 to this bit position.
D5 - BRKD - Break Detect - This is a status bit that is set at the beginning and the end of a break
sequence in the receive data stream. It stays set to 1 until cleared to 0 by writing a 1 to this bit position.
A break signal is a sequence of 0s. When all the required bits, parity bit, wake-up bit, and stop bits are 0x,
the receiver immediately recognizes a break condition (not a framing error) and causes Break Detect
(BRKD) to be set and an interrupt request. At the end of the break signal, a zero character is loaded into
the Receive Data Register (UIOR) and Break Detect is set again, along with another interrupt request.
D6 - CCD - Control Character Detect - This status bit is set any time an ASCII control character is
received in the receive data stream. It stays set until cleared to 0 by writing a 1 to this bit position. (An
ASCII control character is any character that has bits 5 and 6 set to 0.)
D7 - WUD - Wake-Up Detect - This status bit is set any time a valid wake-up condition is detected at the
receiver. It stays set until cleared to 0 by writing a 1 to this bit position. The wake-up condition can be
satisfied in many possible ways by the Wake-up bit, Wake-up Match register, and Wake-Up Mask
register.
Figure 31. UART Interrupt Enable (UIE), R237 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
0
Read/Write
R/W
D0 - RCAIE - Receive Character Available Interrupt Enable - If this bit is set to 1, a Receive
Character Available status in the URC register will cause an interrupt request. In a DMA receive
operation, if this bit is set to 1, an interrupt request will be issued only if an End-of-Process (EOP) of the
DMA counter is also set. If it is not set, a Receive Character Available status causes no interrupt.
D1 - RDMAENB - Receive DMA Enable - When this bit is set to 1, the DMA function is enabled for the
UART receiver. Whenever a Receive Character Available signal in the URC register is true, a DMA
request will be made. When the DMA channel claims control of the bus, it transfers the received data to
the register file or the external memory.
D2 - TIE - Tranmit Interrupt Enable - If this bit is set to 1, a Transmit Buffer Empty signal in the UTC
register will cause an interrupt request. In a DMA transmit operation, if this bit is set to 1, an interrupt
request will be issued only if an End-of-Process (EOP) of the DMA counter is also set. If it is not set, a
Transmit Buffer Empty signal causes no interrupt.
D3 - ZCIE - Zero Count Interrupt Enable - If this bit is set to 1, a baud-rate generator Zero Count
status in the UTC register will cause an interrupt request.
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