- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360677 > I74F50728N (NXP SEMICONDUCTORS) Synchronizing cascaded dual positive edge-triggered D-type flip-flop PDF資料下載
參數(shù)資料
| 型號(hào)： | I74F50728N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronizing cascaded dual positive edge-triggered D-type flip-flop |
| 中文描述： | F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | I74F50728N |
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
5
FUNCTION TABLE
INTERNAL
REGISTER
Q
OUTPUTS
INPUTS
OPERATING MODE
SDn
RDn
CPn
Dn
Qn
Qn
L
H
X
X
H
H
L
Asynchronous set
H
L
X
X
L
L
H
Asynchronous reset
L
L
X
X
X
H
H
Undetermined*
H
H
↑
↑
h
h
H
L
Load ”1”
H
H
l
l
L
H
Load ”0”
H
H
L
X
NC
NC
No change from the previous setup
Don’t care
This setup is unstable and will change when either set of
reset return to the high–level
Low–to–high clock transition.
Data entering the flip–flop requires two clock cycles to
arrive at the output (see logic diagram)
NC
Hold
NOTES:
H =
h =
High voltage level
High voltage level one setup time prior to low–to–high
clock transition
Low voltage level
Low voltage level one setup time prior to low–to–high
clock transition
L
l
=
=
NC=
X =
*
=
↑
=
** =
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
V
IN
I
IN
V
OUT
Supply voltage
–0.5 to +7.0
V
Input voltage
–0.5 to +7.0
V
Input current
–30 to +5
mA
Voltage applied to output in high output state
–0.5 to V
CC
V
I
OUT
Current applied to output in low output state
40
mA
T
amb
Operating free air temperature range
Commercial range
0 to +70
°
C
°
C
°
C
Industrial range
–40 to +85
T
stg
Storage temperature range
–65 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
MIN
NOM
MAX
UNIT
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
Supply voltage
4.5
5.0
5.5
V
High–level input voltage
2.4
V
Low–level input voltage
0.8
V
Input clamp current
–18
mA
High–level output current
–3
mA
Low–level output current
20
mA
°
C
°
C
T
amb
Operating free air temperature range
Commercial range
0
+70
Industrial range
–40
+85
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| I74F50729DB | Dual D-Type Flip-Flop |
| I74F50729D-T | Dual D-Type Flip-Flop |
| I74F50729N-B | Dual D-Type Flip-Flop |
| I74F50729D | Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| I74F50729N | RES,FIXED,MF,243 OHM,1%,0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| I74F50728N-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| I74F50729D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| I74F50729DB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| I74F50729D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| I74F50729N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。