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參數(shù)資料
| 型號： | I74F112N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual J-K negative edge-triggered flip-flop |
| 中文描述： | F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 83K |
| 代理商： | I74F112N |
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
2
February 9, 1990
853–0338 98775
FEATURE
Industrial temperature range available (–40
°
C to +85
°
C)
DESCRIPTION
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop,
feature individual J, K, Clock (CPn), Set (SD) and Reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the Function Table, regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and flip-flop will perform
according to the Function Table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Q1
V
CC
K1
J1
SD1
CP1
RD0
RD1
CP0
K0
Q0
J0
SD0
Q0
9
8
GND
Q1
SF00103
TYPE
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT (TOTAL)
74F112
100MHz
15mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
N74F112N
INDUSTRIAL RANGE
V
CC
= 5V
±
10%, T
amb
= –40
°
C to +85
°
C
I74F112N
PKG DWG #
16-pin plastic DIP
SOT38-4
16-pin plastic SO
N74F112D
I74F112D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
J0, J1
J inputs
1.0/1.0
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/3.0mA
20
μ
A/3.0mA
20
μ
A/2.4mA
K0, K1
K inputs
1.0/1.0
SD0, SD1
Set inputs (active Low)
1.0/5.0
RD0, RD1
Reset inputs (active Low)
1.0/5.0
CP0, CP1
Clock Pulse input (active falling edge)
1.0/4.0
Q0, Q0; Q1, Q1
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
Data outputs
50/33
1.0mA/20mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| I74F113D-T | J-K-Type Flip-Flop |
| I74F113N-B | J-K-Type Flip-Flop |
| I74F113D | Dual J-K negative edge-triggered flip-flops without reset |
| I74F113N | Dual J-K negative edge-triggered flip-flops without reset |
| I74F14D-T | CERAMIC CHIP/MIL-PRF-55681 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| I74F112N,602 | 功能描述:觸發(fā)器 I74F112N/DIP16/TUBE-BULK// RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| I74F112N-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| I74F113D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K negative edge-triggered flip-flops without reset |
| I74F113D,602 | 功能描述:觸發(fā)器 DUAL J-K NEG EDGE F/F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| I74F113D,623 | 功能描述:觸發(fā)器 DUAL J-K NEG EDGE F/F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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