參數(shù)資料
型號(hào)： I5108E
廠商： WINBOND ELECTRONICS CORP
元件分類： 音頻合成
英文描述： SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY
中文描述： 480 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
封裝： 8 X 13.40 MM, PLASTIC, TSOP1-28
文件頁(yè)數(shù)： 69/88頁(yè)
文件大?。?/td> 612K
代理商： I5108E
ISD5100 – SERIES
Publication Release Date: October, 2003
- 69 -
Revision 0.2
Conditions
1.
Typical values: T
A
= 25°C and Vcc = 3.0V.
2.
All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
3.
Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions).
4.
Differential input mode. Nominal differential input is 208 mV p-p. (0TLP)
5.
Sampling frequency can vary as much as –6/+4 percent over the industrial temperature and voltage
ranges. For greater stability, an external clock can be utilized (see Pin Descriptions).
6.
Playback and Record Duration can vary as much as –6/+4 percent over the industrial temperature
and voltage ranges. For greater stability, an external clock can be utilized (See Pin Descriptions).
7.
Filter specification applies to the low pass filter.
8.
For optimal signal quality, this maximum limit is recommended.
9.
When a record command is sent, T
RAC
= T
RAC
+ T
RACL
on the first page addressed.
10.
The maximum signal level at any input is defined as 3.17 dB higher than the reference transmission
level point. (0TLP) This is the point where signal clipping may begin.
11.
Measured at 0TLP point for each gain setting. See the
ANA IN table
and
AUX IN table
on pages 54
and 55 respectively.
12.
0TLP is the reference test level through inputs and outputs. See the
ANA IN table
and
AUX IN table
on pages 54 and 55 respectively.
13.
Referenced to 0TLP input at 1 kHz, measured over 300 to 3,400 Hz bandwidth.
14.
For die, only typical values are applicable.
10.4. C
HARACTERISTICS OF
T
HE
I
2
C S
ERIAL
I
NTERFACE
The I
2
C interface is for bi-directional, two-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a
positive supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not
busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted
as a control signal.
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