參數(shù)資料
型號： HYS72V8200GU-8
廠商： SIEMENS A G
元件分類： DRAM
英文描述： 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
中文描述： 8M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
封裝： DIMM-168
文件頁數(shù)： 8/17頁
文件大?。?/td> 84K
代理商： HYS72V8200GU-8
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Semiconductor Group
8
1998-08-01
Operating Currents
T
A
= 0 to 70
°
C,
V
DD
= 3.3 V
±
0.3 V
1
Recommended Operating Conditions unless otherwise noted
Parameter & Test Condition
Symb.
-8/-8B
-10
Unit
Note
max.
Operating Current
t
RC
=
t
RC(MIN.)
,
t
CK
=
t
CK(MIN.)
Outputs open Burst length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner to maximize
gapless data access
I
CC1
110
75
mA
1
Precharged Standby Current in
Power Down Mode
CS =
V
IH(MIN.)
, CKE
≤
V
IL(MAX.)
t
CK
=
min.
I
CC2P
2
2
mA
1
t
CK
= infinity
I
CC2PS
1
1
mA
1
Precharged Standby Current in
Non-power Down Mode
CS =
V
IH(MIN.)
, CKE
≥
V
IH(MIN.)
t
CK
=
min.
I
CC2N
35
30
mA
1
t
CK
= infinity
I
CC2NS
5
5
1
No operating current
t
CK
= min., CS =
V
IH(MIN.)
,
active state (max. 4 banks)
CKE
≥
V
IH(MIN.)
I
CC3N
45
40
mA
1
CKE
≤
V
IL(MAX.)
I
CC3P
8
8
mA
1
Burst operating current
t
CK
= min.,
Read command cycling
–
I
CC4
70
50
mA
1, 2
Auto refresh current
t
CK
= min.,
Auto Refresh command cycling
–
I
CC5
130
90
mA
1
Self refresh current
Self Refresh Mode, CKE = 0.2 V
standard version
I
CC6
1
1
mA
1
相關PDF資料
PDF描述
HYS72V8200GU-10 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
HYS72V16220GU-10 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
HYS64-74V8200GU Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:10ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes
HYS72V32300GR-75-C2 PC133 Registered SDRAM-Modules
HYS72V128300GR-7-A PC133 Registered SDRAM-Modules
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