參數(shù)資料
型號(hào): HYS72V32200GU-8
廠商: SIEMENS A G
元件分類(lèi): DRAM
英文描述: 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules
中文描述: 32M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
封裝: DIMM-168
文件頁(yè)數(shù): 12/17頁(yè)
文件大小: 84K
代理商: HYS72V32200GU-8
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Semiconductor Group
12
1998-08-01
A serial presence detect storage device - E
2
PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E
2
PROM device during module
production using a serial presence detect protocol (I
2
C synchronous 2-wire bus).
SPD-Table for 256MBit SDRAM based PC100 Modules
Byte#
Description
SPD Entry
Value
Hex
32M
×
64
one bank
-8
32M
×
64
one bank
-8B
32M
×
72
one bank
-8
32M
×
72
one bank
-8B
0
Number of SPD bytes
128
80
80
80
80
1
Total bytes in Serial PD
256
08
08
08
08
2
Memory Type
SDRAM
04
04
04
04
3
Number of Row
Addresses
(without BS bits)
13
0D
0D
0D
0D
4
Number of Column
Addresses (for 32M
×
8
SDRAMs)
10
0A
0A
0A
0A
5
Number of DIMM Banks
1
01
01
01
01
6
Module Data Width
64/72
40
40
48
48
7
Module Data Width
(cont’d)
0
00
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
01
9
SDRAM Cycle Time at
CL = 3
10.0 ns
A0
A0
A0
A0
10
SDRAM Access time
from Clock at CL = 3
6.0 ns
60
60
60
60
11
Dimm Configuration
none / ECC
00
00
02
02
12
Refresh Rate/Type
Self-Refresh,
7.8
μ
s
x8
82
82
82
82
13
SDRAM width, Primary
08
08
08
08
14
Error Checking SDRAM
data width
n/a/x8
00
00
08
08
15
Minimum clock delay for
back-to-back random
column address
t
CCD
= 1 CLK
01
01
01
01
16
Burst Length supported
1, 2, 4, 8 & full
page
8F
8F
8F
8F
17
Number of SDRAM
banks
4
04
04
04
04
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