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參數(shù)資料
| 型號： | HYS72V2100GCU-10 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module |
| 中文描述： | 2M X 72 SYNCHRONOUS DRAM MODULE, 8 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 75K |
| 代理商： | HYS72V2100GCU-10 |
HYS64(72)V2100G(C)U-10
2M x 64/72 SDRAM-Module
Semiconductor Group
9
Notes:
1. The specified values are valid when addresses are changed no more than once during tck(min.)
and when No Operation commands are registered on every rising clock edge during tRC(min).
2. The specified values are valid when data inputs (DQ’) are stable during tRC(min.).
3. An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
4. AC timing tests have V
il
= 0.4 V and V
ih
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V
ih
and V
il
. All AC measurements assume t
T
=1ns
with the AC output load circuit shown.
tCH
5. If clock rising time is longer than 1ns, a time (t
T
/2 -0.5) ns has to be added to this parameter.
6. If t
T
is longer than 1 ns, a time (t
T
-1) ns has to be added to this parameter.
7. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up“the device.
8. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
9. Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
10.t
DAL
is equivalent to t
DPL
+ t
RP
.
1.4V
1.4V
tSETUP
tHOLD
tAC
tAC
tLZ
tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
2.4 V
0.4 V
t
T
fig.1
tCL
相關PDF資料 |
PDF描述 |
|---|---|
| HYS64V2100G | 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module |
| HYS64V2100GU-10 | 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module |
| HYS72V2100GU-10 | 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module |
| HYS64V2200GU-8 | 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| HYS64-72V2200GU-8 | Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:7ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72V2100GU-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module |
| HYS72V2200GU-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| HYS72V2200GU-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| HYS72V2200GU-8-3 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| HYS72V2563201GR-75-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:PC133 Registered SDRAM-Modules |
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