參數(shù)資料
型號(hào): HYS72V16300GR
廠商: INFINEON TECHNOLOGIES AG
英文描述: PC133 Registered SDRAM-Modules
中文描述: PC133的SDRAM的注冊(cè)模塊
文件頁(yè)數(shù): 12/22頁(yè)
文件大?。?/td> 593K
代理商: HYS72V16300GR
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies
12
2002-07-18
Notes
1. The registered DIMM modules are designed to operate under system operating conditions
between 0-55 deg C ambient, maximum sustained bandwidth and 0 LFM airflow. Operating at
higher ambient temperatures needs sufficient air flow to limit the case temperature of the
SDRAM components do not exceed 85
o
C.
2. These parameters depend on the cycle rate. All values are measured at 133 MHz operation
frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents
when tck = infinity.
3. These parameters are measured with continous data stream during read access and all DQ
toggling. CL=3 and BL=4 is assumed and the data-out current is excluded.
4. An initial pause of 100
μ
s is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (
t
STAB
) before
any operation can be guaranteed.
5. AC timing testshave
V
= 0.8 V and
V
= 2.0 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH
and
V
IL
. All AC measurements assume
t
= 1 ns with the AC output load circuit shown. Specified
t
and
t
parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
after the Self Refresh Exit command is registered.
7. Referenced to the time at which the output achieves the open circuit condition, not to output
voltage levels.
Serial Presence Detect
A serial presence detect storage device - E
2
PROM 34C02 - is assembled onto the module.
Information about the module configuration, speed, etc. is written into the E
2
PROM device during
module production using a serial presence detect protocol (I
2
C synchronous 2-wire bus).The first
128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end
user.
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
CLOCK
2.4 V
0.4 V
INPUT
IS
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
IH
t
1.4 V
IO.vsd
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