參數(shù)資料
型號: HYS72V16220GU-8
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
中文描述: 16M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 13/17頁
文件大小: 84K
代理商: HYS72V16220GU-8
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Semiconductor Group
13
1998-08-01
15
Minimum clock
delay for back-to-
back random
column address
t
CCD
= 1
CLK
01
01
01
01
01
01
16
Burst Length
supported
1, 2, 4, 8 &
full page
8F
8F
8F
8F
8F
8F
17
Number of SDRAM
banks
4
04
04
04
04
04
04
18
Supported CAS
Latencies
CAS
latency =
2 & 3
06
06
06
06
06
06
19
CS Latencies
CS
latency = 0
01
01
01
01
01
01
20
WE Latencies
Write
latency = 0
01
01
01
01
01
01
21
SDRAM DIMM
module attributes
non
buffered/
non reg.
V
CC
tol
±
10%
00
00
00
00
00
00
22
SDRAM Device
Attributes: General
06
06
06
06
06
06
23
Min. Clock Cycle
Time at CAS
Latency = 2
10.0/12.0
ns
A0
C0
A0
A0
C0
A0
24
Max. data access
time from Clock for
CL = 2
6.0/7.0 ns
60
70
60
60
60
60
25
Minimum Clock
Cycle Time at
CL = 1
not
supported
FF
FF
FF
FF
FF
FF
26
Maximum Data
Access Time from
Clock at CL = 1
not
supported
FF
FF
FF
FF
FF
FF
27
Minimum Row
Precharge Time
20/30 ns
14
1E
14
14
1E
14
28
Minimum Row
Active to Row
Active delay
t
RRD
16/20 ns
10
14
10
10
14
10
SPD-Table for PC100 Modules
(cont’d)
Byte# Description
SPD
Entry
Value
Hex
16M
×
64
-8
8M
×
64
-8
8M
×
64
-8B
8M
×
72
-8
16M
×
64
-8B
16M
×
72
-8
相關(guān)PDF資料
PDF描述
HYS72V8200GU-8 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
HYS72V8200GU-10 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
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