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參數(shù)資料
| 型號(hào)： | HYS72V16220GU-10 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module |
| 中文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, 8 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大小： | 84K |
| 代理商： | HYS72V16220GU-10 |
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Semiconductor Group
11
1998-08-01
Notes
1. The specified values are valid when addresses are changed no more than once during
t
CK(MIN.)
and when No Operation commands are registered on every rising clock edge during
t
RC(MIN.)
.
Values are shown per module bank.
2. The specified values are valid when data inputs (DQ’s) are stable during
t
RC(MIN.)
.
3. All AC characteristics are shown for device level.
An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
4. AC timing tests have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH
and
V
IL
. All AC measurements assume
t
T
= 1 ns with the AC output load circuit show. Specified
t
AC
and
t
OH
parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1V/ns edge rate
between 0.8 V and 2.0 V.
.
5. If clock rising time is longer than 1ns, a time (
t
T
/2 – 0.5) ns has to be added to this parameter.
6. Rated at 1.5 V
7. If
t
T
is longen than 1 ns, a time (
t
T
– 1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up“ the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
once the Self Refresh Exit command is registered.
10.Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HYS72V16220GU-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module |
| HYS72V16300GR | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:PC133 Registered SDRAM-Modules |
| HYS72V16300GR-7.5-C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|16MX72|CMOS|DIMM|168PIN|PLASTIC |
| HYS72V16300GR-7.5-E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS72V16300GR-75-C | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:PC133 Registered SDRAM-Modules |
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