參數(shù)資料
型號(hào): HYS72V16200GU-8
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules
中文描述: 16M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 8/17頁
文件大?。?/td> 84K
代理商: HYS72V16200GU-8
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Semiconductor Group
8
1998-08-01
Notes
1.
2.
All values are shown per one SDRAM component.
These parameters depend on the cycle rate. These values are measured at 100 MHz for -8
and at 66 MHz for -10 parts. Input signals are changed once during
t
CK
, excepts for
I
CC6
and for
standby currents when
t
CK
= infinity.
These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 is assumed and the
V
DDQ
current is excluded.
3.
Operating Currents
T
A
= 0 to 70
°
C,
V
CC
= 3.3 V
±
0.3 V
1
Recommended Operating Conditions unless otherwise noted
Parameter & Test Condition
Symb.
-8/-8B
-10
Unit Note
max.
Operating current
t
RC
t
RC(MIN.)
,
t
CK
t
CK(MIN.)
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner to maximize
gapless data access
I
CC1
×
4
×
8
×
16
210
210
210
165
165
165
mA
mA
mA
2
Precharged Standby Current in
Power Down Mode
CS =
V
IH(MIN.)
, CKE
V
IL(MAX.)
Precharged Standby Current in Non-
power Down Mode
CS =
V
IH(MIN.)
, CKE
V
IH(MIN.)
No operating current
t
CK
= min., CS =
V
IH(MIN.)
,
active state (max. 4 banks)
t
CK
=
min.
I
CC2P
2
2
mA
2
t
CK
=
min.
I
CC2N
19
16
mA
2
CKE
V
IH(MIN.)
I
CC3N
45
40
mA
2
CKE
V
IL(MAX.)
I
CC3P
10
10
mA
2
Burst operating current
t
CK
= min.,
Read command cycling
I
CC4
×
4
×
8
×
16
I
CC5
210
210
210
165
165
165
mA
mA
mA
2, 3
Auto refresh current
t
CK
= min.,
Auto Refresh command cycling
240
195
mA
2
Self refresh current
Self Refresh Mode, CKE = 0.2 V
standard version
I
CC6
2.5
2.5
mA
2
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