參數(shù)資料
型號(hào)： HYS72T64020HR
廠商： QIMONDA
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 240針DDR2 SDRAM的注冊(cè)模塊
文件頁數(shù)： 25/67頁
文件大?。?/td> 1462K
代理商： HYS72T64020HR
Internet Data Sheet
Rev. 1.21, 2007-03
09152006-J5FK-C565
25
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
19)
t
QHS
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
t
HP
at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
20)
t
=
t
–
t
, where:
t
is the minimum of the absolute half period of the actual input clock; and
t
is the specification value under
the max column. {The less half-pulse width distortion present, the larger the
t
QH
value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides
t
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
t
QH
of 975 ps minimum. 2) If the system
provides
t
HP
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
t
QH
of 1080 ps minimum.
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e.
t
,
t
, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
22) Input waveform timing is referenced from the input signal crossing at the
V
IH.AC
level for a rising signal and
V
IL.AC
for a falling signal applied
to the device under test. See
Figure 3
.
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
t
JIT.PER
,
t
JIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
24) Input waveform timing is referenced from the input signal crossing at the
V
IL.DC
level for a rising signal and
V
IH.DC
for a falling signal applied
to the device under test. See
Figure 3
.
25)
t
RPST
end point and
t
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(
), or begins driving (
t
).
Figure 1
shows a method to calculate these points when the device is no longer driving (
t
), or begins
driving (
t
RPRE
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.PER
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.PER.MIN
= – 72 ps
and
t
JIT.PER.MAX
= + 93 ps, then
t
=
t
+
t
= 0.9 x
t
– 72 ps = + 2178 ps and
t
RPRE.MAX(DERATED)
=
t
RPRE.MAX
+
t
JIT.PER.MAX
t
CK.AVG
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.DUTY.MIN
= – 72 ps
and
t
JIT.DUTY.MAX
= + 93 ps, then
t
=
t
+
t
= 0.4 x
t
– 72 ps = + 928 ps and
t
RPST.MAX(DERATED)
=
t
RPST.MAX
+
t
JIT.DUTY.MAX
t
CK.AVG
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support
t
= RU{
t
PARAM
/
t
CK.AVG
}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
t
nRP
t
}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
RP
= 15 ns, the device will support
t
= RU{
t
/
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
29) DAL = WR + RU{
t
(ns) /
t
(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
t
, if the result
of the division is not already an integer, round up to the next highest integer.
t
refers to the application clock period. Example: For
DDR2–533 at
t
CK
= 3.75 ns with
t
WR
programmed to 4 clocks.
t
DAL
= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
30)
t
DAL.nCK
= WR [nCK] +
t
nRP.nCK
= WR + RU{
t
RP
[ps] /
t
CK.AVG
[ps] }, where WR is the value programmed in the EMR.
31)
t
WTR
is at lease two clocks (2 x
t
CK
) independent of operation frequency.
32)
t
CKE.MIN
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
t
IS
+ 2 x
t
CK
+
t
IH
.
33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from
t
AOND
.
34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD
.
35) When the device is operated with input clock jitter, this parameter needs to be derated by {–
t
–
t
} and {–
t
–
t
} of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter
into a DDR2–667 SDRAM has
t
ERR(6-10PER).MIN
= – 272 ps,
t
ERR(6- 10PER).MAX
= + 293 ps,
t
JIT.DUTY.MIN
= – 106 ps and
t
JIT.DUTY.MAX
= + 94 ps,
then
t
AOF.MIN(DERATED)
=
t
AOF.MIN
+ {–
–
t
} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and
t
AOF.MAX(DERATED)
=
t
AOF.MAX
+ {–
t
JIT.DUTY.MIN
ERR(6-10PER).MIN
} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!)
相關(guān)PDF資料
PDF描述
HYS72T64020HR-2.5-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3.7-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3S-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-5-A 240-Pin Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T64020HR-2.5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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