參數(shù)資料
型號: HYS72T512422HFN-3.7-A
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 240-Pin Fully-Buffered DDR2 SDRAM Modules
中文描述: 512M X 72 DDR DRAM MODULE, PDMA240
封裝: GREEN, DIMM-240
文件頁數(shù): 20/41頁
文件大?。?/td> 985K
代理商: HYS72T512422HFN-3.7-A
Internet Data Sheet
Rev. 1.3, 2006-12
03292006-QQ89-IKE4
20
HYS72T512[4/5]22HFN–[3S/3.7]–A
240-Pin Fully-Buffered DDR2 SDRAM Modules
5
Current Spec. and Conditions
The following table provides an overview of the measurement conditions.
TABLE 13
I
DD
Measurement Conditions
Parameter
Symbol
Idle Current, single or last DIMM
L0 state, idle (0 BW)
Primary channel enabled, Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active
Idle Current, first DIMM
L0 state, idle (0 BW)
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active
Active Power
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled.
DRAM clock active, CKE high.
Active Power, data pass through
L0 state
50% DRAM BW to downstream DIMM, 67% read, 33% write.
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
Training
Primary and Secondary channels enabled.
100% toggle on all channels lanes.
DRAMs idle (0 BW).
CKE high. Command and address lines stable.
DRAM clock active.
IBIST
Over all IBIST modes
DRAM Idle (0 BW)
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Address lines stable
DRAM clock active
I
CC_Idle_0
I
DD_Idle_0
I
CC_Idle_1
I
DD_Idle_1
I
CC_Active_1
I
DD_Active_1
I
CC_Active_2
I
DD_Active_2
I
CC_Training
I
DD_Training
I
CC_IBIST
I
DD_IBIST
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