Internet Data Sheet
Rev. 1.0, 2007-03
03292007-RHOW-C5L6
24
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
TABLE 16
ODT AC Character. and Operating Conditions for DDR2-533
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
t
AOND
t
AON
t
AONPD
t
AOFD
t
AOF
t
AOFPD
t
ANPD
t
AXPD
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
2
t
AC.MIN
t
AC.MIN
+ 2 ns
2.5
t
AC.MIN
t
AC.MIN
+ 2 ns
3
8
2
t
AC.MAX
+ 1 ns
2
t
CK +
t
AC.MAX
+ 1 ns
2.5
t
AC.MAX
+ 0.6 ns
2.5
t
CK +
t
AC.MAX
+ 1 ns
—
—
t
CK
ns
ns
t
CK
ns
ns
t
CK
t
CK
—
1)
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from
t
AOND
, which is interpreted differently per speed bin. For DDR2-400/533,
t
AOND
is 10 ns
(= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if
t
CK
= 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD
. Both are measured from
t
AOFD
, which is interpreted differently per speed bin. For DDR2-400/533,
t
AOFD
is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if
t
CK
= 5 ns.
—
—
2)
—
—
—