參數(shù)資料
型號(hào): HYS72T256420HFD-3.7-A
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 240-Pin Fully-Buffered DDR2 SDRAM Modules
中文描述: 256M X 72 DDR DRAM MODULE, DMA240
封裝: GREEN, DIMM-240
文件頁數(shù): 17/42頁
文件大?。?/td> 1052K
代理商: HYS72T256420HFD-3.7-A
Internet Data Sheet
Rev. 1.2, 2006-11
03292006-GUME-ERC3
17
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
TABLE 10
Supply Voltage Levels and DC Operating Conditions
TABLE 11
Timing Parameters
Parameter
Symbol
Limit Values
Unit
Note
Min.
Nom.
Max.
AMB Supply Voltage
DRAM Supply Voltage
Termination Voltage
EEPROM Supply Voltage
DC Input Logic High(SPD)
DC Input Logic Low(SPD)
DC Input Logic High(RESET)
DC Input Logic Low(RESET)
Leakage Current (RESET)
Leakage Current (Link)
V
CC
V
DD
V
TT
V
DDSPD
V
IH(DC)
V
IL(DC)
V
IH(DC)
V
IL(DC)
I
L
I
L
1.455
1.7
0.48
×
V
DD
3.0
2.1
1.0
–90
–5
1.5
1.8
0.50
×
V
DD
3.3
1.575
1.9
0.52
×
V
DD
3.6
V
DDSPD
0.8
+0.5
+90
+5
V
V
V
V
V
V
V
V
μΑ
μΑ
1)
1) applies for SMB and SPD Bus Signals.
2) applies for AMB CMOS Signal RESET.
3) for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications.
1)
2)
1)
2)
3)
Parameter
Symbol
Min.
Typ.
Max.
Units
Note
EI Assertion Pass-Thru Timing
EI Deassertion Pass-Thru Timing
EI Assertion Duration
FBD Cmd to DDR Clk out that latches Cmd
FBD Cmd to DDR Write
DDR Read to FBD (last DIMM)
Resample Pass-Thru time
ResynchPass-Thru time
Bit Lock Interval
Frame Lock Interval
t
EI Propagate
t
t
EID
t
EI
t
BitLock
t
FrameLock
100
8.1
TBD
5.0
1.075
2.075
4
Bitlock
119
154
clks
clks
clks
ns
ns
ns
ns
ns
frames
frames
2)
1)2)
1) Defined in FB-DIMM Architecture and Protocol Spec
2) Clocks defined as core clocks = 2
×
SCK input
3) @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to
the DRAMs
4) @ DDR2-667 - measured from latest DQS input to AMB to start of matching data frame at northbound FB-DIMM outputs
3)
4)
1)
1)
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