參數(shù)資料
型號(hào)： HYS72T256220HP-3.7-A
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝： GREEN, RDIMM-240
文件頁(yè)數(shù)： 7/49頁(yè)
文件大?。?/td> 1434K
代理商： HYS72T256220HP-3.7-A
Internet Data Sheet
Rev. 1.02, 2007-07
03292006-08VU-L8WK
7
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
220
S2
I
SSTL
Rank 2 is selected by S2
Not Connected
Note: 1-Rank, 2-Ranks module
NC
NC
—
221
S3
I
SSTL
Rank 3 is selected by S3
Not Connected
Note: 1-Rank, 2-Ranks module
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
When sampled at the cross point of the rising edge of CK, and falling
edge of CK, RAS, CAS and WE define the operation to be executed by
the SDRAM.
Register Reset
The RESET pin is connected to the RST pin on the register and to the
OE pin on the PLL. When LOW, all register outputs will be driven LOW
and the PLL clocks to the DRAMs and the register(s) will be set to low-
level. The PLL will remain synchronized with the input clock.
NC
NC
—
192
74
73
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
18
RESET
I
CMOS
Address Signals
71
190
54
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Selects internal SDRAM memory bank
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Not Connected
Less than 1Gb DDR2 SDRAMS
Address Bus 12:0, Address Signal 10/AutoPrecharge
During a Bank Activate command cycle, defines the row address when
sampled at the crosspoint of the rising edge of CK and falling edge of
CK. During a Read or Write command cycle, defines the column
address when sampled at the cross point of the rising edge of CK and
falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is HIGH, autoprecharge is selected and BA[1:0] defines the
bank to be precharged. If AP is LOW, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with
BA[1:0] to control which bank(s) to precharge. If AP is HIGH, all banks
will be precharged regardless of the state of BA[1:0] inputs. If AP is
LOW, then BA[1:0] are used to define which bank to precharge.
NC
I
SSTL
188
183
63
182
61
60
180
58
179
177
70
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
57
176
196
Address Signal 13
Not Connected
Note: Non CA parity modules based on 256 Mbit component
Pin No.
Name
Pin
Type
Buffer
Type
Function
相關(guān)PDF資料
PDF描述
HYS72T256220HP-3S-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64000HP 240-Pin Registered DDR2 SDRAM Modules
HYS72T64000HP-3.7-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64000HP-3S-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T128000HR-3.7-B 240-Pin Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T256220HP-3-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256220HP-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256220HP-3S-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256220HR 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256220HR-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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