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參數(shù)資料
| 型號： | HYS72T256040HP |
| 廠商： | QIMONDA |
| 英文描述： | 240-Pin Registered DDR2 SDRAM Modules |
| 中文描述： | 240針DDR2 SDRAM的注冊模塊 |
| 文件頁數(shù)： | 6/49頁 |
| 文件大小： | 1434K |
| 代理商： | HYS72T256040HP |
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Internet Data Sheet
Rev. 1.02, 2007-07
03292006-08VU-L8WK
6
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
2
Pin Configuration
This chapter contains the pin configuration and block diagrams.
2.1
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in
Table 5
(240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in
Table 6
and
Table 7
respectively. The pin numbering is depicted in
Figure 1
.
TABLE 5
Pin Configuration of RDIMM
Pin No.
Name
Pin
Type
Buffer
Type
Function
Clock Signals
185
186
CK0
CK0
I
I
SSTL
SSTL
Clock Signal CK0, Complementary Clock Signal CK0
The system clock inputs. All address and command lines are sampled
on the cross point of the rising edge of CK and the falling edge of CK.
A Delay Locked Loop (DLL) circuit is driven from the clock inputs and
output timing for read operations is synchronized to the input clock.
Clock Enables 1:0
Activates the DDR2 SDRAM CK signal when HIGH and deactivates
the CK signal when LOW. By deactivating the clocks, CKE0 initiates
the Power Down Mode or the Self Refresh Mode.
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
52
171
CKE0
CKE1
I
I
SSTL
SSTL
NC
NC
—
Control Signals
193
76
S0
S1
I
I
SSTL
SSTL
Chip Select
Enables the associated DDR2 SDRAM command decoder when LOW
and disables the command decoder when HIGH. When the command
decoder is disabled, new commands are ignored but previous
operations continue.
Rank 0 is selected by S0
Rank 1 is selected by S1
The input signals also disable all outputs (except CKE and ODT) of the
register(s) on the DIMM when both inputs are high. When S is HIGH,
all register outputs (except CK, ODT and Chip select) remain in the
previous state.
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
NC
NC
—
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T256040HP-3.7-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256040HP-3S-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256220HP | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256220HP-3.7-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256220HP-3S-A | 240-Pin Registered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T256040HP-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256040HP-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256040HR | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256040HR-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256040HR-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
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