參數(shù)資料
型號： HYS72T256020EU-2.5-B
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 240-Pin unbuffered DDR2 SDRAM Modules
中文描述： 256M X 72 DDR DRAM MODULE, 0.4 ns, DMA240
封裝： GREEN, DIMM-240
文件頁數(shù)： 18/60頁
文件大?。?/td> 1339K
代理商： HYS72T256020EU-2.5-B
Internet Data Sheet
Rev. 1.0, 2006-10
10262006-SX8C-DEY8
18
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 14
Speed Grade Definition Speed Bins for DDR2–533C
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
t
RAS
t
RC
t
RCD
t
RP
45
57
12
12
70000
—
—
—
45
60
15
15
70000
—
—
—
ns
ns
ns
ns
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Speed Grade
DDR2–533C
Unit
Note
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
t
CK
Parameter
Symbol
Min.
Max.
—
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
5
3.75
3.75
45
60
15
15
8
8
8
70000
—
—
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Speed Grade
DDR2–667C
DDR2–667D
Unit
Note
QAG Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
t
CK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
相關(guān)PDF資料
PDF描述
HYS72T256020EU-25F-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3.7-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3S-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020HU-3S-A 240-Pin Unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T256020EU-25F-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3.7-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3S-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020GR 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*