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參數(shù)資料
| 型號： | HYS72T256000HR |
| 廠商： | QIMONDA |
| 英文描述： | 240-Pin Registered DDR SDRAM Modules |
| 中文描述： | 240針DDR SDRAM內(nèi)存模塊注冊 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | HYS72T256000HR |
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Internet Data Sheet
Rev. 1.4, 2007-02
03062006-GD6J-14FP
18
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
t
XP
2
—
nCK
t
XSNR
t
XSRD
WL
t
RFC
+10
200
RL–1
—
—
ns
nCK
nCK
31)
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V. See notes
1)6)1)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
7) The output timing reference voltage level is
V
TT
.
8) New units, ‘
t
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
t
‘ represents the actual
t
of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
t
‘ is used for both concepts. Example:
t
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
t
CK.AVG
+
t
ERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
= – 272
ps and
t
ERR(6- 10PER).MAX
= + 293 ps, then
t
DQSCK.MIN(DERATED)
=
t
DQSCK.MIN
–
t
ERR(6-10PER).MAX
= – 400 ps – 293 ps = – 693 ps and
t
=
–
t
= 400 ps + 272 ps = + 672 ps. Similarly,
t
for DDR2–667 derates to
t
LZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and
t
LZ.DQ.MAX(DERATED)
= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
12)
t
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
t
IS
+ 2 x
t
CK
+
t
IH
.
13) DAL = WR + RU{
t
(ns) /
t
(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
t
, if the result
of the division is not already an integer, round up to the next highest integer.
t
CK
refers to the application clock period. Example: For
DDR2–533 at
t
CK
= 3.75 ns with
t
WR
programmed to 4 clocks.
t
DAL
= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
14)
t
DAL.nCK
= WR [nCK] +
t
nRP.nCK
= WR + RU{
t
RP
[ps] /
t
CK.AVG
[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing
t
with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the
V
IH.DC
level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the
V
IL.DC
level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between
V
IL.DC.MAX
and
V
IH.DC.MIN
Figure 3
.
16)
t
: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e.
t
,
t
, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing
t
with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the
V
level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the
V
IL.AC
level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between
V
il(DC)MAX
and
V
ih(DC)MIN
.
See
Figure 3
.
19) If
t
DS
or
t
DH
is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)
8)
Min.
Max.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T256000HR-3.7-A | 240-Pin Registered DDR SDRAM Modules |
| HYS72T256000HR-3S-A | 240-Pin Registered DDR SDRAM Modules |
| HYS72T256000HR-5-A | 240-Pin Registered DDR SDRAM Modules |
| HYS72T128020EU-2.5-B2 | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T128020EU-25F-B2 | 240-Pin unbuffered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T256000HR-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules |
| HYS72T256000HR-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules |
| HYS72T256000HR-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules |
| HYS72T256020EU-2.5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T256020EU-25F-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
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