參數(shù)資料
型號(hào)： HYS72T256000HR-5-A
廠商： QIMONDA AG
元件分類(lèi)： DRAM
英文描述： 240-Pin Registered DDR SDRAM Modules
中文描述： 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封裝： GREEN, DIMM-240
文件頁(yè)數(shù)： 16/40頁(yè)
文件大?。?/td> 1050K
代理商： HYS72T256000HR-5-A
Internet Data Sheet
Rev. 1.4, 2007-02
03062006-GD6J-14FP
16
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3
AC Characteristics
3.3.1
Speed Grades Definitions
TABLE 11
Speed Grade Definition
3.3.2
AC Timing Parameters
TABLE 12
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Speed Grade
DDR2–667
DDR2–533C
DDR2–400B
Unit
Note
QAG Sort Name
–3S
–3.7
–5
CAS-RCD-RP latencies
5–5–5
4–4–4
3–3–3
t
CK
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
—
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
5
3.75
3
45
60
15
15
8
8
8
70000
—
—
—
5
3.75
3.75
45
60
15
15
8
8
8
70000
—
—
—
5
5
5
40
55
15
15
8
8
8
70000
—
—
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)
8)
Min.
Max.
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
t
AC
t
CCD
t
CH.AVG
t
CK.AVG
–450
2
0.48
3000
+450
—
0.52
8000
ps
nCK
t
CK.AVG
ps
9)
10)11)
相關(guān)PDF資料
PDF描述
HYS72T128020EU-2.5-B2 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020EU-25F-B2 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020EU-3.7-B2 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020EU-3-B2 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020EU-3S-B2 240-Pin unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T256020EU-2.5-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-25F-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3.7-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3S-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*