參數(shù)資料
型號(hào)： HYS72T256000ER
廠商： QIMONDA
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 240針DDR2 SDRAM的注冊模塊
文件頁數(shù)： 16/33頁
文件大?。?/td> 892K
代理商： HYS72T256000ER
Internet Data Sheet
Rev. 1.0, 2006-10
10202006-EHWJ-OT02
16
HYS72T256000ER-[3.7/5]-B
Registerd DDR2 SDRAM Module
3.3.2
Component AC Timing Parameters
Timing Parameters:
Table 14
for DDR2–533C and
Table 15
for DDR2–400B
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
t
RC
t
RCD
t
RP
55
15
15
—
—
—
ns
ns
ns
1)2)3)4)
1)2)3)4)
1)2)3)4)
Parameter
Symbol
DDR2–533
Unit
Note
1)2)3)4)5)
6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ and DM input hold time (single ended data
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
t
AC
t
CCD
t
CH
t
CKE
t
CL
t
DAL
–500
2
0.45
3
0.45
WR +
t
RP
+500
—
0.55
—
0.55
—
ps
t
CK
t
CK
t
CK
t
CK
t
CK
8)18)
t
DELAY
t
IS
+
t
CK
+
t
IH
––
ns
9)
t
DH
(base)
225
––
ps
10)
t
DH1
(base)
–25
—
ps
11)
t
DIPW
t
DQSCK
t
DQSL,H
t
DQSQ
0.35
–450
0.35
—
—
+
450
—
300
t
CK
ps
t
CK
ps
11)
t
DQSS
– 0.25
+ 0.25
t
CK
Speed Grade
DDR2–400B
Unit
Note
QAG Sort Name
–5
CAS-RCD-RP latencies
3–3–3
t
CK
Parameter
Symbol
Min.
Max.
—
相關(guān)PDF資料
PDF描述
HYS72T256000ER-3.7-B 240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-5-B 240-Pin Registered DDR2 SDRAM Modules
HYS72T256020EU-2.5-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-25F-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3.7-B 240-Pin unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T256000ER-3.7-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-5-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256000HR 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules
HYS72T256000HR-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules
HYS72T256000HR-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules
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