參數(shù)資料
型號(hào)： HYS72T128300HP-3.7-A
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 128M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝： GREEN, DIMM-240
文件頁(yè)數(shù)： 22/50頁(yè)
文件大?。?/td> 1423K
代理商： HYS72T128300HP-3.7-A
Internet Data Sheet
Rev. 1.22, 2007-06
07042006-834B-Z31V
23
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 2
Method for calculating transitions and endpoint
FIGURE 3
Differential input waveform timing -
t
DS
and
t
DS
32)
t
RPST
end point and
t
RPRE
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(
), or begins driving (
t
).
Figure 2
shows a method to calculate these points when the device is no longer driving (
t
), or begins
driving (
t
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.PER.MIN
= – 72 ps
and
t
JIT.PER.MAX
= + 93 ps, then
t
=
t
+
t
= 0.9 x
t
– 72 ps = + 2178 ps and
t
RPRE.MAX(DERATED)
=
t
RPRE.MAX
+
t
JIT.PER.MAX
t
CK.AVG
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
34) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.DUTY.MIN
= – 72 ps
and
t
JIT.DUTY.MAX
= + 93 ps, then
t
RPST.MIN(DERATED)
=
t
RPST.MIN
+
t
JIT.DUTY.MIN
= 0.4 x
t
CK.AVG
– 72 ps = + 928 ps and
t
RPST.MAX(DERATED)
=
t
RPST.MAX
+
t
JIT.DUTY.MAX
= 0.6 x
t
CK.AVG
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
35) For these parameters, the DDR2 SDRAM device is characterized and verified to support
t
nPARAM
= RU{
t
PARAM
/
t
CK.AVG
}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
t
nRP
= RU{
/
t
}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
= 15 ns, the device will support
t
nRP
= RU{
t
RP
/
t
CK.AVG
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
36)
t
WTR
is at lease two clocks (2 x
t
CK
) independent of operation frequency.
W+=
W5367
HQGSR LQW
7 7
92+[P
9
92+[P
9
92/ [P
9
92/ [P 9
W/=
W535(
EHJLQSRLQW
7
7
977 [P9
977 [P9
977 [ P9
977 [P9
W/= W535(
EHJLQSRL QW
7 7
W+=W53 67
HQGSRL QW
7 7
W'6
9
''4
9
,+D F
PL Q
9
,+G F
PL Q
6
2%&DC
9
,/ GF
PD [
9
,/ DF
PD [
9
66
'46
'46
W'+
W'6
W'+
相關(guān)PDF資料
PDF描述
HYS72T128300HP-3S-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T128320HP-3.7-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T128320HP-3S-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T128320HP-5-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64300HP-3.7-A 240-Pin Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T128300HP-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128320HP-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128320HP-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128320HP-5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128420HFA-3S-B 功能描述:MODULE DDR2 1GB 240-DIMM RoHS:是 類別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM
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