參數(shù)資料
型號(hào): HYS72T128020HU-2.5-B
廠(chǎng)商: QIMONDA AG
元件分類(lèi): DRAM
英文描述: 240-Pin unbuffered DDR2 SDRAM Modules
中文描述: 128M X 72 DDR DRAM MODULE, 0.4 ns, DMA240
封裝: GREEN, UDIMM-240
文件頁(yè)數(shù): 30/87頁(yè)
文件大?。?/td> 1723K
代理商: HYS72T128020HU-2.5-B
Internet Data Sheet
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
30
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
13) The
t
HZ
,
t
RPST
and
t
LZ
,
t
RPRE
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(
t
t
), or begins driving (
t
t
).
t
and
t
transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85
°
C
and 95
°
C.
15) 0 °C
T
CASE
85
°
C
16) 85
°
C
<
T
CASE
95
°
C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The
t
timing parameter depends on the page size of the DRAM organization. See
Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4
.
19) The maximum limit for the
t
parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum
t
WTR
is two clocks when operating the DDR2-SDRAM at frequencies
≤ 200 ΜΗ
z.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing
t
XARD
can be used. In “l(fā)ow active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing
t
XARDS
has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the
t
timing parameter, where
WR
[cycles] =
t
(ns)/
t
(ns) rounded
up to the next integer value.
t
= WR + (
t
/
t
). For each of the terms, if not already an integer, round to the next highest integer.
t
CK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
相關(guān)PDF資料
PDF描述
HYS72T128020HU-25F-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020HU-3.7-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020HU-3-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020HU-3S-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020HU-5-B 240-Pin unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T128020HU-25F-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020HU-3.7-A 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T128020HU-3.7-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020HU-37-A 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T128020HU-3-A 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules