參數(shù)資料
型號: HYS72T128020HP-3.7-A
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 240-Pin Registered DDR2 SDRAM Modules
中文描述: 128M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: GREEN, RDIMM-240
文件頁數(shù): 18/49頁
文件大?。?/td> 1434K
代理商: HYS72T128020HP-3.7-A
Internet Data Sheet
Rev. 1.02, 2007-07
03292006-08VU-L8WK
18
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
RAS-CAS-Delay
Row Precharge Time
t
RCD
t
RP
15
15
ns
ns
1)2)3)4)
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
Speed Grade
DDR2–533C
Unit
Note
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
t
CK
Parameter
Symbol
Min.
Max.
相關(guān)PDF資料
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HYS72T128020HP-3S-A 240-Pin Registered DDR2 SDRAM Modules
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