參數(shù)資料
型號(hào): HYS72T128020HFA-3S-B
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 240-Pin Fully-Buffered DDR2 SDRAM Modules
中文描述: 128M X 72 DDR DRAM MODULE, DMA240
封裝: GREEN, DIMM-240
文件頁(yè)數(shù): 3/47頁(yè)
文件大?。?/td> 1378K
代理商: HYS72T128020HFA-3S-B
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Internet Data Sheet
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
3
1
Overview
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
1.1
Features
240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM
Module for PC, Workstation and Server main memory
applications.
One rank 64M
×
72 and , two rank 128M
×
72, 256M
×
72
module organization, and 64M
×
8, 128M
×
4 chip
organization
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
2GB, 1GB, 512MB Modules built with chipsize packages
PG-TFBGA-60
Re-drive and re-sync of all address, command, clock and
data signals using AMB (Advanced Memory Buffer).
High-Speed Differential Point-to-Point Link Interface at 1.5
V (Jedec standard pending).
Host Interface and AMB component industry standard
compliant.
Supports SMBus protocol interface for access to the AMB
configuration registers.
Detects errors on the channel and reports them to the host
memory controller.
Automatic DDR2 DRAM Bus Calibration.
Automatic Channel Calibration.
Full Host Control of the DDR2 DRAMs.
Over-Temperature Detection and Alert.
Hot Add-on and Hot Remove Capability.
MBIST and IBIST Test Functions.
Transparent Mode for DRAM Test Support.
Low profile: 133.35mm x 30.35 mm
240 Pin gold plated card connector with 1.00mm contact
centers (JEDEC standard pending).
Based on JEDEC standard reference card designs (Jedec
standard pending).
SPD (Serial Presence Detect) with 256 Byte serial
E
2
PROM.Performance:
RoHS Compliant Products
1)
TABLE 1
Performance Table
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
QAG Speed Code
–2.5
–3S
–3.7
Unit
DRAM Speed Grade
DDR2–800E
DDR2–667D
DDR2–533C
Module Speed Grade
PC2–6400E
PC2–5300D
PC2–4200C
CAS-RCD-RP latencies
6–6–6
5–5–5
4–4–4
Max. Clock Frequency
CL3
CL5
CL4
CL6
f
CK3
f
CK5
f
CK4
f
CK6
t
RCD
t
RP
200
333
266
400
15
15
200
333
266
15
15
200
266
266
15
15
MHz
MHz
MHz
MHz
ns
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
相關(guān)PDF資料
PDF描述
HYS72T256020HFA 240-Pin Fully-Buffered DDR2 SDRAM Modules
HYS72T256020HFA-2.5-B 240-Pin Fully-Buffered DDR2 SDRAM Modules
HYS72T256020HFA-3.7-B 240-Pin Fully-Buffered DDR2 SDRAM Modules
HYS72T256020HFA-3S-B 240-Pin Fully-Buffered DDR2 SDRAM Modules
HYS72T64400HFA 240-Pin Fully-Buffered DDR2 SDRAM Modules
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參數(shù)描述
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