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參數(shù)資料
| 型號： | HYS72T128000HR-5-B |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 240-Pin Registered DDR2 SDRAM Modules |
| 中文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | GREEN, RDIMM-240 |
| 文件頁數(shù)： | 18/52頁 |
| 文件大?。?/td> | 1250K |
| 代理商： | HYS72T128000HR-5-B |
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Internet Data Sheet
Rev. 1.2, 2007-01
03292006-JXZQ-CG6T
18
HYS72T[64/128/256]xxxHR–[3S/3.7/5]–B
240-Pin Registered DDR2 SDRAM
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
0
°
C
≤
T
CASE
≤
85
°
C
85
°
C
≤
T
CASE
≤
95
°
C
Read preamble
Read postamble
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V. See notes
5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
7) The output timing reference voltage level is
V
TT
.
8) New units, ‘
t
CK.AVG
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
t
CK.AVG
‘ represents the actual
t
CK.AVG
of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
t
‘ is used for both concepts. Example:
t
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
t
CK.AVG
+
t
ERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
ERR(6-10PER).MIN
= – 272
ps and
t
ERR(6- 10PER).MAX
= + 293 ps, then
t
DQSCK.MIN(DERATED)
=
t
DQSCK.MIN
–
t
ERR(6-10PER).MAX
= – 400 ps – 293 ps = – 693 ps and
t
=
–
t
= 400 ps + 272 ps = + 672 ps. Similarly,
t
for DDR2–667 derates to
t
LZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and
t
LZ.DQ.MAX(DERATED)
= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
12)
t
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
t
IS
+ 2 x
t
CK
+
t
IH
.
t
QH
t
QHS
t
REFI
t
HP
–
t
QHS
—
—
340
ps
ps
26)
27)
–
–
0.9
0.4
7.5
0.35
0.4
15
7.5
2
7 – AL
7.8
3.9
1.1
0.6
—
—
0.6
—
—
—
—
μ
s
—
t
RPRE
t
RPST
t
RTP
t
WPRE
t
WPST
t
WR
t
WTR
t
XARD
t
XARDS
t
CK.AVG
t
CK.AVG
ns
t
CK.AVG
t
CK.AVG
ns
ns
nCK
nCK
28)29)
28)30)
1)
—
—
1)
1)31)
—
t
XP
2
—
nCK
—
t
XSNR
t
XSRD
WL
t
RFC
+10
200
RL–1
—
—
ns
nCK
nCK
1)
—
—
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)
8)
Min.
Max.
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|---|---|
| HYS72T128020HR-3.7-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128020HR-3S-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128020HR-5-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256220HR-3.7-B | 240-Pin Registered DDR2 SDRAM Modules |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T128001HR | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules |
| HYS72T128001HR-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules |
| HYS72T128020EU-2.5-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T128020EU-25F-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T128020EU-3.7-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
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