參數(shù)資料
型號(hào)： HYS72D64500GR-8-B
廠商： INFINEON TECHNOLOGIES AG
英文描述： Registered DDR SDRAM-Modules
中文描述： 注冊(cè)DDR SDRAM內(nèi)存模塊
文件頁(yè)數(shù)： 35/39頁(yè)
文件大?。?/td> 1036K
代理商： HYS72D64500GR-8-B
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Application Note
Data Sheet
35
Rev. 1.03 2004-01
6
Application Note
Power Up and Power Management on DDR Registered DIMMs
(according to JEDEC ballot JC-42.5 Item
1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and
to minimize power consumption during low power mode. One feature is externally controlled via a system-
generated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked
Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM
inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the
register outputs are forced to a low level, and all differential register input receivers are powered down, resulting
in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as
an asynchronous signal according to the attached details. Using this function also permits the system and DIMM
clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh
mode.
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until
activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz
or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating
frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual
detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made
High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less than
1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied
inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Registered
DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-
bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control
CKE to one physical DIMM bank through the use of the RESET pin.
Table 16
RESET Truth Table
Register Inputs
Register
Outputs
Data out (Q)
H
L
Qo
Illegal input
conditions
L
RESET
H
H
H
H
CK
Rising
Rising
L or H
High Z
CK
Data in (D)
H
L
X
X
Falling
Falling
L or H
High Z
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
X: Don’t care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling
相關(guān)PDF資料
PDF描述
HYS72T128020HU-37-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS64T128020HU-37-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS64T64000HU-37-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T64000HU-37-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS64T32000HU-37-A 240-Pin Unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T128000GR 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
HYS72T128000GR-37-A 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
HYS72T128000GR-5-A 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
HYS72T128000HP 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128000HP-2.5-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*