參數(shù)資料
型號: HYS72D64320GU-6-B
廠商: INFINEON TECHNOLOGIES AG
英文描述: 184-Pin Unbuffered Dual-In-Line Memory Modules
中文描述: 184引腳緩沖雙列內存模組
文件頁數(shù): 22/42頁
文件大?。?/td> 976K
代理商: HYS72D64320GU-6-B
342
765
810
1080
1440
13
25
1620
1935
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Data Sheet
22
Rev. 1.0, 2004-03
AC Characteristic
Table 17
Parameter
Table 16
I
DD
Specification for PC2700
H
128MB
256MB
×
64
×
64
1 Rank
1 Rank
–6
–6
Typ.
Max.
Typ.
260
300
480
320
380
560
16
20
32
100
340
200
68
96
136
44
60
88
144
180
256
340
400
560
360
440
600
480
640
960
6
11
11
720
860
1440
P
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
H
H
H
H
256MB
×
72
1 Rank
–6
Typ.
540
630
36
225
153
99
288
630
675
H
H
512MB
×
64
2 Ranks
–6
Typ.
736
816
64
400
272
176
512
816
856
1216 1584
44
1696 2024
H
H
512MB
×
72
2 Ranks
–6
Typ.
828
918
72
450
306
198
576
918
963
1368
25
1908
H
Unit
Note
1)2)
1) Module
I
DD
values are calculated on the basis of component
I
DD
and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values:
V
DD
= 2.7 V,
T
A
= 10 °C
3) The module
I
DDx
values are calculated from the
I
DDx
values of the component data sheet as follows:
m
×
I
DDx
[component] +
n
×
I
DD3N
[component] with
m
and
n
number of components of rank 1 and 2;
n
=0 for 1 rank modules
4) DQ I/O (
I
DDQ
) currents are not included in the calculations (see note 1)
5) The module
I
DDx
values are calculated from the corrponent
I
DDx
data sheet values as: (
m
+
n
)
×
I
DDx
[component]
Max.
600
680
40
240
192
120
304
680
720
1280
22
1720
Max.
675
765
45
270
216
135
Max.
904
984
80
480
384
240
608
984
1024
Max.
1017
1107
90
540
432
270
684
1107
1152
1782
25
2277
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)
3)4)
5)
5)
5)
5)
5)
3)4)
3)
3)
22
5)
3)4)
AC Timing - Absolute Specifications for PC3200 and PC2700
Symbol –6
–5
DDR400B
Min.
–0.5
–0.6
0.45
0.45
min. (
t
CL
,
t
CH
)
Unit Note/ Test
Condition
1)
DDR333
Min.
–0.7
–0.6
0.45
0.45
min. (
t
CL
,
t
CH
)
Max.
+0.7
+0.6
0.55
0.55
Max.
+0.5
+0.6
0.55
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
t
AC
t
DQSCK
t
CH
t
CL
t
HP
ns
ns
t
CK
t
CK
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
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