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參數(shù)資料
| 型號： | HYS72D64300HU-5-B |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 184-Pin Unbuffered Dual-In-Line Memory Modules |
| 中文描述： | 184引腳緩沖雙列內(nèi)存模組 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大小： | 1374K |
| 代理商： | HYS72D64300HU-5-B |
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HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Data Sheet
20
Rev. 1.0, 2004-05
10042003-RYU3-RQON
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Exit self-refresh to non-read command
t
XSNR
Exit self-refresh to read command
Average Periodic Refresh Interval
t
RRD
10
—
12
—
ns
2)3)4)5)
t
WR
t
DAL
15
—
15
—
ns
t
CK
2)3)4)5)
2)3)4)5)11)
t
WTR
2
75
200
—
—
—
—
7.8
1
75
200
—
—
—
—
7.8
t
CK
ns
t
CK
μ
s
2)3)4)5)
2)3)4)5)
t
XSRD
t
REFI
2)3)4)5)
2)3)4)5)12)
1) 0
°
C
≤
T
A
≤
70
°
C
; V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V
(DDR400)
2) Input slew rate
≥
1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between
V
IH(ac)
and
V
IL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 13
Parameter
AC Timing - Absolute Specifications for PC3200 and PC2700
Symbol
–5
DDR400B
Min.
–6
DDR333
Min.
Unit
Note/ Test
Condition
1)
Max.
Max.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HYS72D64300HU-5-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Unbuffered Double Data Rate SDRAM |
| HYS72D64300HU-6-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS72D64300HU-6-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Unbuffered Double Data Rate SDRAM |
| HYS72D64301 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184 - Pin Registered Double-Data-Rate SDRAM Module |
| HYS72D64301GBR-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184 - Pin Registered Double-Data-Rate SDRAM Module |
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