參數(shù)資料
型號: HYS72D64300GU-6-B
廠商: INFINEON TECHNOLOGIES AG
英文描述: 184-Pin Unbuffered Dual-In-Line Memory Modules
中文描述: 184引腳緩沖雙列內(nèi)存模組
文件頁數(shù): 6/40頁
文件大?。?/td> 1374K
代理商: HYS72D64300GU-6-B
Data Sheet
6
Rev. 1.0, 2004-05
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
HYS64D64300[G/H]U–[5/6]–B
HYS72D64300[G/H]U–[5/6]–B
HYS64D128320[G/H]U–[5/6]–B
HYS72D128320[G/H]U–[5/6]–B
1
Overview
1.1
Features
184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Workstation main
memory applications
One rank 64M x 64, 64M
×
72 and two ranks 128M
×
64, 128M
×
72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (
±
0.2V) power supply
Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E
2
PROM
JEDEC standard MO-206 form factor: 133.35 mm
×
31.75 mm
×
4.00 mm max.
Jedec standard reference layout
Gold plated contacts
DDR400 speed grade supported
Lead-free
Table 1
Performance
1.2
Description
The HYS64D64300[G/H]U–[5/6]–B, HYS72D64300[G/H]U–[5/6]–B, HYS64D128320[G/H]U–[5/6]–B, and
HYS72D128320[G/H]U–[5/6]–B are industry standard 184-Pin Unbuffered Dual-In-Line Memory Modules
(UDIMM) organized as 64M
×
64, 128M
×
64 for non-parity and 64M
×
72,128M
×
72 for ECC main memory
applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of
decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD)
based on a serial E
2
PROM device using the 2-pin I
2
C protocol. The first 128 bytes are programmed with
Part Number Speed Code
Speed Grade
–5
DDR400B
PC3200–3033
200
166
133
6
DDR333B
PC2700–2533
166
166
133
Unit
MHz
MHz
MHz
Component
Module
@CL3
@CL2.5
@CL2
max. Clock Frequency
f
CK3
f
CK2.5
f
CK2
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