- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370807 > HYS72D64300GBR-6-C (INFINEON TECHNOLOGIES AG) Aluminum Polymer Radial Lead Capacitor; Capacitance: 560uF; Voltage: 4V; Case Size: 8x12 mm; Packaging: Bulk PDF資料下載
參數(shù)資料
| 型號： | HYS72D64300GBR-6-C |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Aluminum Polymer Radial Lead Capacitor; Capacitance: 560uF; Voltage: 4V; Case Size: 8x12 mm; Packaging: Bulk |
| 中文描述： | 184針注冊雙倍數(shù)據(jù)速率SDRAM模塊 |
| 文件頁數(shù)： | 23/38頁 |
| 文件大?。?/td> | 1121K |
| 代理商： | HYS72D64300GBR-6-C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet
23
Rev. 1.0, 2004-03
07302003-2MI6-FOP1
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command period
t
RC
Auto-refresh to Active/Auto-refresh command
period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
t
RPRE
t
RPST
t
RAS
0.9
0.40
40
55
70
1.1
0.60
70E+3
—
—
0.9
0.40
42
60
72
1.1
0.60
70E+3
—
—
t
CK
t
CK
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
RFC
2)3)4)5)
t
RCD
t
RP
t
RAP
t
RRD
t
WR
t
DAL
15
15
t
RCD
or
t
RASmin
10
15
(
t
WR
/
t
CK
)+(
t
RP
/
t
CK
)
—
—
18
18
—
—
ns
ns
ns
ns
ns
t
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
—
—
12
15
—
—
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
t
WTR
t
XSNR
t
XSRD
t
REFI
2
75
200
—
—
—
—
7.8
1
75
200
—
—
—
—
7.8
t
CK
ns
t
CK
μ
s
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
1) 0
°
C
≤
T
A
≤
70
°
C
; V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V
(DDR400)
2) Input slew rate
≥
1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between
V
IH(ac)
and
V
IL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 12
Parameter
AC Timing - Absolute Specifications for PC3200 and PC2700
Symbol –5
–6
DDR333
Min.
Unit Note/ Test
Condition
1)
DDR400B
Min.
Max.
Max.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72D32300GBR-6-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300GBR-5-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D32300GBR-5-C | Aluminum Polymer Radial Lead Capacitor; Capacitance: 820uF; Voltage: 2.5V; Case Size: 8x12 mm; Packaging: Bulk |
| HYS72D32300GBR | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64320HU-5-C | 184-Pin Unbuffered Dual-In-Line Memory Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D64300GBR-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184 - Pin Registered Double Data Rate SDRAM Modules |
| HYS72D64300GBR-7-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300GU-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:42184-Pin Unbuffered Double-Data-Rate Memory Modules |
| HYS72D64300GU-6-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS72D64300HBR-5-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double Data Rate SDRAM Module |
發(fā)布緊急采購，3分鐘左右您將得到回復。