參數(shù)資料
型號(hào)： HYS72D64000GU-7-A
廠商： INFINEON TECHNOLOGIES AG
英文描述： 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
中文描述： 2.5伏184針緩沖的DDR - SDRAM內(nèi)存模塊我
文件頁數(shù)： 16/18頁
文件大小： 302K
代理商： HYS72D64000GU-7-A
HYS64/72D64000/128020GU-7/8-A
Unbuffered DDR-I SDRAM-Modules
INFINEON Technologies
16
2002-09-10 (rev.0.81)
SPD Codes for PC2100 & PC2700 Modules “-7” & “-6”
512MB
x64
1bank
-7
HE
X
80
08
07
0D
0B
01
40
00
04
70
75
00
82
08
00
512MB
x72
1bank
-7
HE
X
80
08
07
0D
0B
01
48
00
04
70
75
02
82
08
08
1GB
x64
2bank
-7
HE
X
80
08
07
0D
0B
02
40
00
04
70
75
00
82
08
00
1GB
x72
2bank
-7
HE
X
80
08
07
0D
0B
02
48
00
04
70
75
02
82
08
08
1GB
x64
2bank
-6
HE
X
80
08
07
0D
0B
02
40
00
04
60
70
00
82
08
00
1GB
x72
2bank
-6
HE
X
80
08
07
0D
0B
02
48
00
04
60
70
02
82
08
08
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 2.5
Access Time from Clock at CL = 2.5
DIMM Config
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-Back
Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 2
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1.5
Access Time from Clock at CL = 1.5
Minimum Row Precharge Time
Minimum Row Act. to Row Act. Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
Addr. and Command Setup Time
Addr. and Command Hold Time
Data Input Setup Time
Data Input Hold Time
Superset Information
Minimum Core Cycle Time tRC
Min. Auto Refresh Cmd Cycle Time tRFC
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew tDQSQ
X
-Factor tQHS
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
128
256
DDR-SDRAM
13
11
1 / 2
x64 / x72
0
SSTL_2.5
7 ns
0.75 ns
non-ECC / ECC
Self-Refresh, 7.8 ms
x8
na / x8
15
tccd = 1 CLK
01
01
01
01
01
01
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
2, 4 & 8
4
0E
04
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
F3
C1
INFI-
NEON
0E
04
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
05
C1
INFI-
NEON
0E
04
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
F4
C1
INFI-
NEON
0E
04
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
06
C1
INFI-
NEON
0E
04
0C
01
02
20
C0
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
42
C1
INFI-
NEON
0E
04
0C
01
02
20
C0
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
54
C1
INFI-
NEON
CAS latency = 2 & 2.5
CS latency = 0
Write latency = 1
unbuffered
–
7.5 ns
0.75 ns
not supported
not supported
20 ns
15 ns
20 ns
45 ns
512MByte
0.9 ns
0.9 ns
0.5 ns
0.5 ns
–
65 ns
75 ns
12 ns
0.5 ns
0.75 ns
–
Revision 0.0
–
–
36-40
41
42
43
44
45
46-61
62
63
64
65-71
Manufacturer
–
72
Module Assembly Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
–
–
–
–
–
–
–
73-90
91-92
93-94
95-98
99-127
128-255
open for Customer use
–
Byte#
Description
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HYS64D64000GU-8-A 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72D64000GU-8-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
HYS72D64020GR-7-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules
HYS72D64020GR-7-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules
HYS72D64020GR-8-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules
HYS72D64020GR-8-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules
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