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參數(shù)資料
| 型號： | HYS72D128521GR-7F-B |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | TRIMMER, 100R |
| 中文描述： | 注冊DDR SDRAM內(nèi)存模塊 |
| 文件頁數(shù)： | 20/39頁 |
| 文件大小： | 1036K |
| 代理商： | HYS72D128521GR-7F-B |
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HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
Data Sheet
20
Rev. 1.03 2004-01
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes
were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in
progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between
V
OH(ac)
and
V
OL(ac)
.
11)
t
RPRES
is defined for CL = 1.5 operation only
12) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
13) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D128521GR-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Low Profile Registered DDR-I SDRAM-Modules |
| HYS72D128900HBR-6-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double-Data-Rate SDRAM Module |
| HYS72D16000GR | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Registered DDR SDRAM-Modules |
| HYS72D16000GR-7-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Registered DDR SDRAM-Modules |
| HYS72D16000GR-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Registered DDR SDRAM-Modules |
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