參數(shù)資料
    型號(hào): HYS64V16302GU-7-D
    廠商: INFINEON TECHNOLOGIES AG
    英文描述: 3.3 V 16M 】 64-Bit, 128MByte SDRAM Module 168-pin Unbuffered DIMM Modules
    中文描述: 3.3伏1,600】64位,128MByte SDRAM內(nèi)存模塊168針腳無(wú)緩沖DIMM模塊
    文件頁(yè)數(shù): 1/13頁(yè)
    文件大小: 89K
    代理商: HYS64V16302GU-7-D
    INFINEON Technologies
    1
    9.01
    HYS 64V16302GU
    SDRAM-Modules
    3.3 V 16M
    ×
    64-Bit, 128MByte SDRAM Module
    168-pin Unbuffered DIMM Modules
    Description
    The HYS 64V16302 is an industry standard 168-pin 8-byte Dual in-line Memory Module (DIMM)
    which is organized as 16M
    ×
    64 in an one bank high speed memory arrays designed with 256 Mbit
    Synchronous DRAMs for non-parity applications. The DIMMs use -7 speed sorted 16M
    ×
    16
    organised 256Mbit SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, -
    7.5 for PC133-333 and -8 parts for the standard PC100 applications. Decoupling capacitors are
    mounted on the PC board. The PC board design is according to INTEL’s module specification.
    The DIMMs have a serial presence detect, implemented with a serial E2PROM using the 2-pin I
    2
    C
    protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
    available to the end user.
    All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm
    long footprint.
    Important Notice:
    This module, which is based on 256MBit device technology can only be used in applications, where
    the 256Mbit addressing is supported.
    168 Pin unbuffered 8 Byte Dual-In-Line
    SDRAM Modules for PC main memory
    applications using 256Mbit technology
    PC100-222, PC133-333 and PC133-222
    versions
    One bank 16M
    ×
    64 organization
    Optimized for byte-write non-parity
    JEDEC standard Synchronous DRAMs
    (SDRAM)
    Single 3.3 V (
    ±
    0.3 V) power supply
    SDRAM Performance:
    Programmed Latencies:
    Programmable CAS Latency, Burst Length,
    and Wrap Sequence
    (Sequential & Interleave)
    Auto Refresh (CBR) and Self Refresh
    Decoupling capacitors mounted on substrate
    All inputs and outputs are LVTTL compatible
    Serial Presence Detect with E
    2
    PROM
    Utilizes 16M
    ×
    16 (256Mbit SDRAMs in
    TSOPII-54 packages with
    8096 refresh cycles every 64 ms
    133.35 mm
    ×
    29.21 mm
    ×
    3.00 mm card size
    with gold contact pads
    (JEDEC MO-161)
    -7/ -7.5 -8
    Unit
    PC133
    PC100
    f
    CK
    Clock
    Frequency
    (max.)
    133
    100
    MHz
    t
    AC
    Clock Access
    Time
    5.4
    6
    ns
    Product Speed
    CL
    t
    RCD
    2
    t
    RP
    2
    -7
    PC133
    2
    -7.5
    PC133
    3
    3
    3
    -8
    PC100
    2
    2
    2
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