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| 型號(hào)： | HYS64D64000GU-8-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
| 中文描述： | 2.5伏184針緩沖的DDR - SDRAM內(nèi)存模塊我 |
| 文件頁(yè)數(shù)： | 14/18頁(yè) |
| 文件大小： | 302K |
| 代理商： | HYS64D64000GU-8-A |
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HYS64/72D64000/128020GU-7/8-A
Unbuffered DDR-I SDRAM-Modules
INFINEON Technologies
14
2002-09-10 (rev.0.81)
t
RFC
Auto-refresh to Active/Auto-refresh
command period
72
75
80
ns
1-4
t
RCD
Active to Read or Write delay
18
20
20
ns
1-4
t
RP
Precharge command period
18
20
20
ns
1-4
t
RRD
Active bank A to Active bank B command
12
15
15
ns
1-4
t
WR
Write recovery time
15
15
15
ns
1-4
t
DAL
Auto precharge write recovery
+ precharge time
(twr/tck)
+ (trp/
tck)
(twr/tck)
+ (trp/
tck)
t
CK
1-4,9
t
WTR
Internal write to read command delay
1
1
1
t
CK
1-4
t
X
SNR
Exit self-refresh to non-read command
75
75
80
ns
1-4
t
X
SRD
Exit self-refresh to read command
200
200
200
t
CK
1-4
t
REFI
Average Periodic
Refresh Interval
512 Mbit based
7.8
7.8
7.8
μ
s
1-4, 8
1. Input slew rate
>
=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V
REF.
CK/CK slew rate are
>
= 1.0 V/ns.
3. Inputs are not recognized as valid until V
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
TT
.
5. t
and t
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (H
Z
), or begins driving (L
Z
).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-
Z
to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate
>
= 1.0 V/ns , slow slew rate
>
= 0.5 V/ns and
<
1V/ns for command/address and CK & CK slew rate
>
1.0 V/
ns, measured between VOH(ac) and VOL(ac)
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0
°
C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V
;
V
DD
= 2.5V
±
0.2V)
Symbol
Parameter
DDR333
-6
DDR266A
-7
DDR200
-8
Unit
Notes
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72D64000GU-8-A | 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
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| HYS72D128300GBR-6-B | Category 6 Termination Kit; Contents Of Kit:GigaBIX? mount, color-coded GigaBIX? connectors, wire guards, designation strips and labels, Velcro tie and installation guide RoHS Compliant: Yes |
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