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參數(shù)資料
| 型號： | HYS 64V8301GU |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3 V 8M *64/72-Bit SDRAM Modules(3.3 V 8M×64/72-Bit 同步動態(tài)RAM 模塊) |
| 中文描述： | 3.3伏800萬* 64/72-Bit內存模塊（3.3伏8米× 64/72-Bit同步動態(tài)內存模塊） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 92K |
| 代理商： | HYS 64V8301GU |
HYS 64V8301GU
SDRAM-Modules
Data Book
9
12.99
8. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
9. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieved the open circuit condition, not to
output voltage levels.
A serial presence detect storage device - E
2
PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E
2
PROM device during module
production using a serial presence detect protocol (I
2
C synchronous 2-wire bus).
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS64V8301GU-7.5-C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYS64V8301GU-7.5-C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYS64V8301GU-7-C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|8MX64|CMOS|DIMM|168PIN|PLASTIC |
| HYS64V8301GU-8-C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYS64V8301GU-8-C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
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