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參數(shù)資料
| 型號： | HYMP112S64MP8-E3 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | SCREW LOCKS MALE |
| 中文描述： | 128M X 64 DDR DRAM MODULE, 0.6 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, DIMM-200 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 405K |
| 代理商： | HYMP112S64MP8-E3 |
HYMP112S64(L)MP8
Rev. 0.1/ July 2004
12
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
AC Timing Parameters by Speed Grade
Speed
DDR2-533(C4)
DDR2-533(C5)
DDR2-400(C3)
DDR2-400(C4)
Unit
Bin(CL-tRCD-tRP)
4-4-4
5-5-5
3-3-3
4-4-4
Parameter
min
min
min
min
CAS Latency
4
5
3
4
ns
tRCD
15
18.75
15
20
ns
tRP
15
18.75
15
20
ns
tRC
60
63.75
55
65
ns
tRAS
45
45
40
45
ns
Parameter
Symbol
DDR2-400
DDR2-533
Unit
Note
Min
Max
Min
Max
Data-Out edge to Clock edge Skew
tAC
-600
600
-500
500
ps
DQS-Out edge to Clock edge Skew
tDQSCK
-500
500
-500
450
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
System Clock Cycle Time
tCK
5000
8000
3750
8000
ps
DQ and DM input hold time
tDH
400
-
350
-
ps
1
DQ and DM input setup time
tDS
400
-
350
-
ps
1
Control & Address input Pulse Width for
each input
tIPW
0.6
-
0.6
-
tCK
DQ and DM input pulse witdth for each input
pulse width for each input
tDIPW
0.35
-
0.35
-
tCK
Data-out high-impedance window
from CK, /CK
tHZ
-
tAC max
-
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ
signals
tLZ(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
ps
tDQSQ
-
350
-
300
ps
DQ hold skew factor
DQ/DQS output hold time from DQS
tQHS
tQH
-
450
-
-
400
-
ps
ps
tHP - tQHS
tHP - tQHS
Write command to first DQS latching
transition
tDQSS
WL - 0.25
WL + 0.25
WL - 0.25
WL + 0.25
tCK
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.35
0.35
-
-
0.35
0.35
-
-
tCK
tCK
DQS falling edge to CK setup time
DQS falling edge hold time from CK
tDSS
tDSH
0.2
0.2
-
-
0.2
0.2
-
-
tCK
tCK
Mode register set command cycle time
tMRD
2
-
2
-
tCK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYMP112S64MP8-E4 | SCREW LOCKS FEMALE SETS |
| HYS72D64300HBR-5-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HBR-6-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HBR-7-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64320 | 184-Pin Registered Double Data Rate SDRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYMP112S64MP8-E4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:DDR2 SDRAM SO-DIMM |
| HYMP112U64CP8-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-Y5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
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