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參數(shù)資料
| 型號(hào)： | HYMP112S64MP8-C5 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | SCREW LOCKS MALE |
| 中文描述： | DDR2 SDRAM的SO - DIMM插槽 |
| 文件頁(yè)數(shù)： | 8/17頁(yè) |
| 文件大?。?/td> | 405K |
| 代理商： | HYMP112S64MP8-C5 |
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HYMP112S64(L)MP8
Rev. 0.1/ July 2004
8
Differential Input AC logic Level
Note:
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS
and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS,
LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to
VIH(DC) - V IL(DC).
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK,
DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to
VIH(AC) - V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations
in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
Differential AC output parameters
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track
variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Symbol
Parameter
Min.
Max.
Units
Notes
V
ID
(ac)
ac differential input voltage
0.5
VDDQ + 0.6
V
1
V
IX
(ac)
ac differential cross point voltage
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
Symbol
Parameter
Min.
Max.
Units
Notes
V
OX
(ac)
ac differential cross point voltage
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
V
DDQ
Crossing point
V
SSQ
V
TR
V
CP
V
ID
V
IX or
V
OX
< Differential signal levels >
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYMP112S64MP8-E3 | SCREW LOCKS MALE |
| HYMP112S64MP8-E4 | SCREW LOCKS FEMALE SETS |
| HYS72D64300HBR-5-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HBR-6-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HBR-7-C | 184-Pin Registered Double Data Rate SDRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYMP112S64MP8-E3 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver. |
| HYMP112S64MP8-E4 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:DDR2 SDRAM SO-DIMM |
| HYMP112U64CP8-C4 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S5 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S6 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
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