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參數(shù)資料
| 型號(hào)： | HYM72V64M636BLF8 |
| 英文描述： | 64Mx64|3.3V|K/H|x8|SDR SDRAM - SO DIMM 512MB |
| 中文描述： | 64Mx64 | 3.3 |鉀/ ? | x8 | SDRAM的特別提款權(quán)-蘇512MB的內(nèi)存 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 215K |
| 代理商： | HYM72V64M636BLF8 |
PC133 SDRAM Registered DIMM
Rev. 0.4/Dec. 2002
13
HYM72V12C736B(L)S4 Series
AC CHARACTERISTICS II
Note :
1. Timing delay due to the register is considered in a registered DIMM
2. A new command can be given tRRC after self refresh exit
Parameter
Symbol
-K
-H
Unit
Note
Min
Max
Min
Max
RAS Cycle Time
Operation
tRC
60
-
65
-
ns
Auto Refresh
tRRC
60
-
65
-
ns
RAS to CAS Delay
tRCD
15
-
20
-
ns
RAS Active Time
tRAS
45
100K
45
100K
ns
RAS Precharge Time
tRP
15
-
20
-
ns
RAS to RAS Bank Active Delay
tRRD
15
-
15
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
CLK
Data-In to Precharge Command
tDPL
2
-
2
-
CLK
Data-In to Active Command
tDAL
5
-
5
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
CLK
Precharge to Data
Output Hi-Z
CAS Latency = 3
tPROZ3
3
-
3
-
CLK
CAS Latency = 2
tPROZ2
2
-
2
-
CLK
Power Down Exit Time
tPDE
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
CLK
1
Refresh Time
tREF
-
64
-
64
ms
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