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參數(shù)資料
| 型號(hào)： | HYM71V8M755HCLFU6 |
| 英文描述： | 8Mx72|3.3V|8/P/S|x5|SDR SDRAM - SO DIMM 64MB |
| 中文描述： | 8Mx72 | 3.3 | 8/P/S | X5的| SDRAM的特別提款權(quán)-蘇64MB的內(nèi)存 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 355K |
| 代理商： | HYM71V8M755HCLFU6 |
PC133 SDRAM Unbuffered DIMM
Rev. 0.1/Nov. 01
3
HYM71V32635BT8 Series
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CK0~CK3
Clock Inputs
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE0, CKE1
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
/S0 ~ /S3
Chip Select
Enables or disables all inputs except CK, CKE and DQM
BA0, BA1
SDRAM Bank Address
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
/RAS, /CAS, /WE
Row Address Strobe, Column
Address Strobe, Write Enable
/RAS, /CAS and /WE define the operation
Refer function truth table for details
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ63
Data Input/Output
Multiplexed data input / output pin
VCC
Power Supply (3.3V)
Power supply for internal circuits and input buffers
V
SS
Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
SA0~2
SPD Address Input
Serial Presence Detect Address Input
WP
Write Protect for SPD
Write Protect for Serial Presence Detect on DIMM
NC
No Connection
No connection
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