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參數資料
| 型號： | HYM71V8M655AT6-P |
| 英文描述： | x64 SDRAM Module |
| 中文描述： | X64的內存模塊 |
| 文件頁數： | 10/14頁 |
| 文件大?。?/td> | 355K |
| 代理商： | HYM71V8M655AT6-P |
PC133 SDRAM Unbuffered DIMM
Rev. 0.1/Nov. 01
11
HYM71V32635BT8 Series
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Parameter
Symbol
-K
-H
Unit
Note
Min
Max
Min
Max
System Clock
Cycle Time
CAS Latency = 3
tCK3
7.5
1000
7.5
1000
ns
CAS Latency = 2
tCK2
7.5
10
ns
Clock High Pulse Width
tCHW
2.5
-
2.5
-
ns
1
Clock Low Pulse Width
tCLW
2.5
-
2.5
-
ns
1
Access Time
From Clock
CAS Latency = 3
tAC3
-
5.4
-
5.4
ns
2
CAS Latency = 2
tAC2
-
5.4
-
6
ns
Data-Out Hold Time
tOH
2.7
-
2.7
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
ns
1
CKE Setup Time
tCKS
1.5
-
1.5
-
ns
1
CKE Hold Time
tCKH
0.8
-
0.8
-
ns
1
Command Setup Time
tCS
1.5
-
1.5
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1
-
1
-
ns
CLK to Data
Output in High-Z
Time
CAS Latency = 3
tOHZ3
2.7
5.4
2.7
5.4
ns
CAS Latency = 2
tOHZ2
2.7
5.4
3
6
ns
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HYM71V8M655AT6-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYM71V8M655ATU6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx64|3.3V|P/S|x4|SDR SDRAM - SO DIMM 64MB |
| HYM71V8M655BLT6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx64|3.3V|8/P/S|x4|SDR SDRAM - SO DIMM 64MB |
| HYM71V8M655BT6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx64|3.3V|8/P/S|x4|SDR SDRAM - SO DIMM 64MB |
| HYM71V8M655HCLT6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx64|3.3V|8/P/S|x4|SDR SDRAM - SO DIMM 64MB |
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