參數(shù)資料
型號(hào): HYM322160S
廠商: SIEMENS AG
英文描述: 2M x 32-Bit Dynamic RAM Module
中文描述: 200萬(wàn)× 32位動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊
文件頁(yè)數(shù): 9/9頁(yè)
文件大?。?/td> 142K
代理商: HYM322160S
Semiconductor Group
559
Notes:
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are measured with the output open.
4) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles out of which at least one cycle
has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
5)
V
(min.)
and
V
(max.)
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
IH
and
V
IL
.
6) Measured with a load equivalant of 2 TTL loads and 100 pF.
7)
t
OFF
(max.)
defines the time at which the output achieves the open-circuit condition and is not referenced to
output voltage levels.
8) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9) These parameters are referenced to the CAS leading edge.
10)
t
WCS
is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only.
If
t
WCS
>
t
WCS
(min.)
, the cycle is an early write cycle and data out pin will remain open circuit (high impedance).
11) Operation within the
t
(max.)
limit insures that
t
RAC
(max.)
can be met.
t
(max.)
is specified as a reference
point only. If
t
RCD
is greater than the specified
t
RCD
(max.)
limit, then access time is controlled by
t
CAC .
12) Operation within the
t
(max.)
limit insures that
t
RAC
(max.)
can be met.
t
(max.)
is specified as a reference
point only. If
t
RAD
is greater than the specified
t
RAD
(max.)
limit, then access time is controlled by
t
AA .
13)For CAS-before-RAS cycles only.
HYM 322160S/GS-60/-70
2M x 32-Bit
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