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參數資料
| 型號： | HYE18P32161ACL85 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-DTL-38999 Series II; Body Material:Metal; Series:JT; No. of Contacts:11; Connector Shell Size:18; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
| 中文描述： | 32M的異步/頁的CellularRAM |
| 文件頁數： | 15/33頁 |
| 文件大?。?/td> | 641K |
| 代理商： | HYE18P32161ACL85 |
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Data Sheet
15
V2.0, 2003-12-16
HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Functional Description
2.2
Access To The Control Register Map
Write-only access to the refresh control register is enabled by applying the SCR command and asserting the ZZ-
pin to low.
Figure 5
shows the mapping of the address bus lines to the the refresh control register bits, whereas
in Figure 6 the access timing is illustrated.
Figure 5
Refresh Control Registers
Figure 6
Control Register Write Access Protocol
PASR
refreshed memory area
A2
A1
A0
Partial Array Self Refresh
0
0
1
0
1
0
A0
entire memory array (def.)
0
0
0
A1
A2
A3
A4
A5
A6
A7
A8
A18
A20
TCSR
PM
0
0
0
max. case temp.
A5
Temperature-Compensated
Self-Refresh
1
+85°C (def.)
+70°C
+45°C
+15°C
0
1
0
A6
1
0
0
1
control reg
Control Register Select
A19
RCR
reserved
0
1
Address Bus
Control Register
power down
Deep Power Down Mode
enabled
disabled (def.)
0
1
A4
0
1
1
lower 1/2 of memory array
lower 1/4 of memory array
lower 1/8 of memory array
1
0
1
1
1
0
1
1
1
upper 1/2 of memory array
upper 1/4 of memory array
upper 1/8 of memory array
DPD
0
zero
1
0
0
page mode
Page Mode Bit
disabled (def.)
enabled
0
1
A7
A19
0
A20, A18....A8, A3:
reserved, must be set to '0'.
Don't Care
A20-A0
RCR OPCODE
CS1
WE
UB, LB
DQ15-DQ0
ZZ
Initiate Control Register
Access
Open Latch
Close Latch
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