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參數(shù)資料
| 型號： | HYB514256BJ-60 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| 中文描述： | 256K X 4 FAST PAGE DRAM, 60 ns, PDSO20 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 215K |
| 代理商： | HYB514256BJ-60 |
Semiconductor Group
64
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
×
4-DRAM
Notes :
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
,
I
CC6
and
I
CC7
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are measured with the output open.
4) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles before proper device operation
is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles
instead of 8 RAS cycles are required.
5)
V
(min.) and
V
(max.) are reference levels for measuring timing of input signals. Transition times are also
measured between
V
IH
and
V
IL
.
6) Measured with a load equivalent to 2 TTL loads and 100 pF.
7)
t
(max.) and
t
(max.) define the time at which the output achieves the open-circuit conditions and is not
referenced to output voltage levels.
8) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-modify-write cycles.
10)
t
,
t
,
t
and
t
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
≥
t
(min.), the cycle is an early write cycle and data out pin will remain
open circuit (high impedance) through the entire cycle; if
t
≥
t
(min.),
t
≥
t
(min.) and
t
≥
t
(min.), the cycle is a read-modify-write cycle and I/O will contain data read from the selected cell. If neither of
the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
11) Operation within the
t
(max.) limit insures that
t
RAC
(max.) can be met,
t
RCD
(max.) is specified as a reference
point only. If
t
RCD
is greater than the specified
t
RCD
t
CAC
.
12) Operation within the
t
(max.) limit insures that
t
RAC
(max.) can be met.
t
RAD
(max.) is specified as a reference
point only. If
t
RAD
is greater than the specified
t
RAD
t
AA
.
13) AC measurements assume
t
T
= 5ns.
14) Either
t
DZC
or
t
DZO
must be satisfied.
15) Either
t
CDD
or
t
ODD
must be satisfied.
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PDF描述 |
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| HYB514256BJ-70 | 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| HYB514256BJL-50 | 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| HYB514256BJL-60 | 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| HYB514256BJL-70 | 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| HYB514256BL-50 | 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB514256BJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| HYB514256BJ-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| HYB514256BJL-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| HYB514256BJL-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| HYB514256BJL-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
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