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參數(shù)資料
| 型號： | HYB39S256400DTL-8 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-MBit Synchronous DRAM |
| 中文描述： | 256兆位同步DRAM |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 630K |
| 代理商： | HYB39S256400DTL-8 |
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HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Functional Description
Data Sheet
15
Rev. 1.02, 2004-02
10072003-13LE-FGQQ
3.2
Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power
on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a
conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During
power on, all
V
DD
and
V
DDQ
pins must be built up simultaneously to the specified voltage when the input signals
are held in the “NOP” state. The power on voltage must not exceed
V
DD
+0.3V on any of the input pins or
V
DD
supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 ms is required
followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all
banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A
minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming
the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
3.3
Mode Register Definition
The Mode register designates the operation mode at the read or write cycle. This register is divided into four fields.
First, a Burst Length Field which sets the length of the burst, Second, an Addressing Selection bit which programs
the column access sequence in a burst cycle (interleaved or sequential). Third, a CAS Latency
Field to set the
access time at clock cycle. Fourth, an Operation mode field to differentiate between normal operation (Burst read
and burst Write) and a special Burst Read and Single Write mode. After the initial power up, the mode set
operation must be done before any activate command. Any content of the mode register can be altered by re-
executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock
before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals
of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
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| HYB39S64160BT-8 | Safety Goggle; Pack Quantity:1 RoHS Compliant: NA |
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相關(guān)代理商/技術(shù)參數(shù) |
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| HYB39S256400FE-7 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-MBit Synchronous DRAM |
| HYB39S256400FEL-7 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-MBit Synchronous DRAM |
| HYB39S256400FF-7 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-MBit Synchronous DRAM |
| HYB39S256400FFL-7 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-MBit Synchronous DRAM |
| HYB39S256400FT-7 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-MBit Synchronous DRAM |
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